[Chisel] Don't use polymorphism

What I want to do

• There are multiple similar units

• Most of processes are the same, only some differences.

• Select an appropriate unit depending on the conditions and execute the process

What I tried to do

To achieve this

• Define the parent class and write common processing here

• Each unit is defined as a child class that inherits the above, and its own processing is written here.

• Decide which unit to execute the process

• Define a variable that represents the "unit to execute". The type is the parent class.

• The selected unit is assigned to the "unit to execute" and the process is executed.

This is what I tried to do. So called polymorphism.

class UnitBase{

}

class Unit1 extends UnitBase{

}

class Unit2 extends UnitBase{

}

val selectedUnit = Module(new UnitBase)
when(...){
  selectedUnit := Module(new Unit1)  //※
}

However, this will result in a compilation error saying "type is different" at the *. The chisel compiler seems to be strict in type checking.

Solution

Just like the previous case of " I want to exit the loop midway ," this also occurs because the idea is not considered from the perspective of "how to operate the hardware."

Real circuits don't work like "there is one slot for an 'execution unit and one of units is assigned to it depending on the conditions."

To achieve "what I want to do", I should do like below

• Connect all the necessary signals to all units.

• "valid signal" indicating "whether or not processing should be performed" is prepared additionally.

• Turn on the valid signal of the selected unit
  

class UnitBase{
  val io = IO(new Bundle {
    val sig = Input(UInt(32.W))
    val enb = Input(Bool())
  }
}

val units:Seq[UnitBase] = Seq(Module(new Unit1), Module(new Unit2))
Seq.tabule(4){i => {
    units(i).sig := ...
    units(i).enb := Mux(..., ture.B, false.B)
  }
}